從Pascal到Blackwell的執行緒分歧特徵化

摘要

自Volta架構引入獨立執行緒排程（ITS）以來，NVIDIA GPU普遍被認為以固定方式處理執行緒分歧。我們以ITS之前的Pascal架構為基準，在Ampere、Hopper以及資料中心與消費級Blackwell GPU上測試此假設。結合週期精確的微基準測試、硬體計數器以及編譯器產生的SASS靜態分析，我們區分出穩定行為與架構變遷。在所有測試世代中，分歧路徑的序列化時間與路徑數k呈線性關係，遵循T(k) ≈ s×k，且無超線性再聚合懲罰。執行緒執行效率下降為32/k，此懲罰與佔用率無關，而預測執行消除了序列化成本。相同行為亦見於Pascal，顯示此程式設計師可見的成本模型早在ITS之前即已存在。然而，編譯器發出的再聚合機制已有大幅改變：Pascal使用基於每執行緒的SSY/SYNC指令堆疊，而後續世代則改用屏障暫存器指令；超過立即後支配節點的延遲再聚合案例，從Ampere的29個降至Blackwell的2個。Blackwell亦引入雙層聚合屏障分類、均勻分支指令，以及明確的部分遮罩執行緒同步——這些機制在Ampere或Hopper上均未出現。受控位元翻轉實驗指出，新的屏障分類屬於編譯器靜態分類，在我們的測試中無可觀察的運行時效應。因此，即使NVIDIA的控制流ISA與再聚合機制持續演化，分歧仍維持穩定且可預測的效能成本。

English

Since Volta introduced Independent Thread Scheduling (ITS), NVIDIA GPUs have been widely assumed to handle warp divergence in a fixed manner. We test this assumption across Ampere, Hopper, and datacenter and consumer Blackwell GPUs, using pre-ITS Pascal as a baseline. Combining cycle-accurate microbenchmarks, hardware counters, and static analysis of compiler-generated SASS, we separate stable behavior from architectural change. Across all tested generations, divergent paths serialize linearly with the number of paths k, following T(k) approx sk with no super-linear reconvergence penalty. Warp execution efficiency falls as 32/k, the penalty is independent of occupancy, and predication removes the serialization cost. The same behavior appears on Pascal, showing that this programmer-visible cost model predates ITS. The compiler-emitted reconvergence machinery, however, has changed substantially. Pascal uses a per-warp SSY/SYNC instruction stack, whereas later generations use barrier-register instructions. Deferred reconvergence beyond the immediate post-dominator falls from 29 cases on Ampere to 2 on Blackwell. Blackwell also introduces a two-tier convergence-barrier classification, uniform-branch instructions, and explicit partial-mask warp synchronization, none of which appear on Ampere or Hopper. Controlled bit-flip experiments indicate that the new barrier class is a static compiler classification with no observable runtime effect in our tests. Thus, divergence retains a stable and predictable performance cost even as NVIDIA's control-flow ISA and reconvergence mechanisms continue to evolve.