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面向边缘设备低延迟脑电图分类的可微逻辑门网络

Differentiable Logic Gate Networks for Low-Latency EEG Classification on Edge Devices

July 20, 2026
作者: Shyamal Y. Dharia, Stephen D. Smith, Camilo E. Valderrama
cs.AI

摘要

边缘设备上的实时脑电图分类受限于传统神经网络中的浮点运算。本研究探索了可微分逻辑门网络作为硬件原生替代方案,该方案将模型编译为可通过CPU位运算执行的纯布尔逻辑电路。通过在四个脑电图数据集(涵盖二分类痴呆检测和三分类情绪识别两种任务)上进行严格的等参数实验,我们在四个复杂度等级(5万至50万参数)下,将Diff-Logic与同等容量的多层感知机和二值化神经网络基线进行了对比。在痴呆筛查任务中,Diff-Logic的宏F1值达到80.2%,较MLP基线提升了6.8%。在情绪识别任务中,MLP虽然保持适度性能优势,但在功耗受限(7瓦)的Nvidia Jetson Orin Nano CPU(单核)上部署时,其延迟增加了2.3倍,模型体积扩大了14倍。关键发现是,当模型规模扩大10倍时,Diff-Logic的推理时间几乎保持不变,在最大复杂度等级上较MLP实现了2.9倍的峰值加速。我们的研究结果确立了基于逻辑的神经架构作为资源受限脑机接口的实用范式,能够在满足便携式边缘部署的延迟和内存约束的同时,实现具有竞争力或更优的性能。代码已开源:https://github.com/Shyamal-Dharia/eeg-difflogic
English
Real-time EEG classification on edge devices is bottlenecked by the floating-point arithmetic of conventional neural networks. We investigated Differentiable Logic Gate Networks (Diff-Logic) as a hardware-native alternative that compiles models into pure Boolean circuits executable via bitwise CPU operations. Through rigorous iso-parameter experiments across four EEG datasets spanning two classification tasks, binary dementia detection and 3-class emotion recognition, we compared Diff-Logic against matched-capacity Multi-Layer Perceptron (MLP) and Binarized Neural Network (BNN) baselines at four complexity tiers (50k-500k parameters). On dementia screening, Diff-Logic achieved 80.2% Macro F1, outperforming the MLP baseline by 6.8%. On emotion recognition, the MLP retained a moderate performance advantage but incurred a 2.3times higher latency and 14times larger model size when deployed on a power-constrained (7W) Nvidia Jetson Orin Nano CPU (Single-core). Critically, Diff-Logic inference time remained nearly constant across a 10times increase in model scale, achieving a peak speedup of 2.9times over MLPs at the largest complexity tier. Our results establish logic-based neural architectures as a practical paradigm for resource-constrained brain-computer interfaces, achieving competitive or superior performance while natively satisfying the latency and memory constraints of portable edge deployment. Code is available on GitHub: https://github.com/Shyamal-Dharia/eeg-difflogic