EvolVE：基于大语言模型的Verilog生成与优化进化搜索

摘要

Verilog的设计流程本质上是劳动密集型的，且需要深厚的领域专业知识。尽管大语言模型为实现自动化提供了可行路径，但其有限的训练数据和固有的顺序推理模式难以捕捉硬件系统严格的形式化逻辑与并发特性。为突破这些限制，我们提出了EvolVE——首个在芯片设计任务中分析多种进化策略的框架，发现蒙特卡洛树搜索在最大化功能正确性方面表现卓越，而思想引导优化法则在电路优化方面更具优势。我们进一步利用结构化测试平台生成技术加速进化过程。针对复杂优化基准缺失的问题，我们推出了源自全国集成电路竞赛产业级赛题的IC-RTL基准集。评估结果表明，EvolVE在VerilogEval v2和RTLLM v2上分别达到98.1%和92%的准确率，确立了最新技术标杆。在产业级IC-RTL测试中，本框架优于竞赛选手编写的参考实现：哈夫曼编码的功耗-性能-面积乘积最高降低66%，所有赛题的几何平均值优化幅度达17%。IC-RTL基准集源代码已发布于https://github.com/weiber2002/ICRTL。

English

Verilog's design cycle is inherently labor-intensive and necessitates extensive domain expertise. Although Large Language Models (LLMs) offer a promising pathway toward automation, their limited training data and intrinsic sequential reasoning fail to capture the strict formal logic and concurrency inherent in hardware systems. To overcome these barriers, we present EvolVE, the first framework to analyze multiple evolution strategies on chip design tasks, revealing that Monte Carlo Tree Search (MCTS) excels at maximizing functional correctness, while Idea-Guided Refinement (IGR) proves superior for optimization. We further leverage Structured Testbench Generation (STG) to accelerate the evolutionary process. To address the lack of complex optimization benchmarks, we introduce IC-RTL, targeting industry-scale problems derived from the National Integrated Circuit Contest. Evaluations establish EvolVE as the new state-of-the-art, achieving 98.1% on VerilogEval v2 and 92% on RTLLM v2. Furthermore, on the industry-scale IC-RTL suite, our framework surpasses reference implementations authored by contest participants, reducing the Power, Performance, Area (PPA) product by up to 66% in Huffman Coding and 17% in the geometric mean across all problems. The source code of the IC-RTL benchmark is available at https://github.com/weiber2002/ICRTL.

EvolVE：基于大语言模型的Verilog生成与优化进化搜索

EvolVE: Evolutionary Search for LLM-based Verilog Generation and Optimization

摘要

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